You will be challenged by the complexity and difficulty of designing/verifying the high density memory chip (up to 8Gb) with huge scale of circuit capability (over 4M transistors), ultra high speed (clock cycle is less than 1ns), complicated functionality (DDR4, LPDDR4), advanced low power and power management technology.
Provide support to design engineers, simulate, analyze and debug current chip designs.
Co-work with international colleagues on developing new verification tools and flows for the verification difficulties on DRAM chip。
Familiar with analog/digital simulation tools, ie. HSPICE, HSIM, VerilogHDL, FINESIM
Must possess good communication skills and ability to work well in a team
Experience in SV, VPI coding preferred
Gate Level circuit design preferred
Experience in UVM Test Bench preferred
Previous work experience in DRAM memory related fields a plus
English language skill in writing and speaking is a must
BS or MS in Electrical Engineering is required